The present invention relates to a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, and a method for manufacturing the same.
For an insulated gate field effect transistor (metal insulator semiconductor FET (MISFET)) such as a MOSFET, the combination of a gate insulating film composed of silicon oxide and a gate electrode formed of a polycrystalline silicon film is widely used. For example, in a CMOS semiconductor device, there is a need for an N-channel MOSFET (hereinafter, referred to simply as NMOS) and a P-channel MOSFET (hereinafter, referred to simply as PMOS) included in the CMOS semiconductor device to have threshold voltages that are sufficiently low and symmetric with each other. Even for MOSFETs of which gate length is 0.1 μm or smaller, a gate electrode having the optimum work function value can be formed for each of an NMOS and PMOS by forming the gate electrode by using polycrystalline silicon and adjusting an impurity in the gate electrode and the concentration thereof.
Presently, miniaturization of transistors is being advanced based on the so-called scaling rule, and thereby enhancement in the integration degree and the operating speed of semiconductor devices is being promoted. For miniaturization of an insulated gate field effect transistor, it may be required to suppress the influence of the so-called short-channel effect. As long as a gate electrode is composed of a semiconductor material, it may be impossible to effectively suppress the depletion of the gate electrode, which is one of factors in the short-channel effect. To address this, there has been proposed a scheme in which a gate electrode is formed by using a conductive material such as a metal or metal nitride. As schemes for forming a gate electrode by using a conductive material, there has been proposed a method in which e.g. a metal film is deposited instead of a polycrystalline silicon film and a gate electrode is formed by pattering this metal film similarly to existing methods. Furthermore, there has also been proposed a method in which a gate electrode is formed by a so-called damascene process of burying the electrode in a gate electrode formation opening (refer to e.g., Atsushi Yagishita et al., “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime”, International Electron Devices Meeting 1998 Technical Digest pp. 785 to 788 (1998)). In the method of forming a gate electrode by a damascene process, a gate insulating film composed of an insulating material (e.g., hafnium oxide) of which relative dielectric constant is higher than that of silicon oxide is formed in a gate electrode formation opening arising from removal of a dummy gate, and then a gate electrode is formed. In this damascene process, various kinds of heat treatment (e.g., annealing treatment for activation of an impurity in source/drain regions) have been completed before the formation of the gate electrode. Therefore, mobility deterioration and so on hardly occur, and thus an insulated gate field effect transistor having enhanced characteristics can be provided.
Different kinds of insulated gate field effect transistors, such as an NMOS and PMOS, typically have different optimum work function values of gate electrodes. In a configuration in which the gate electrode of an NMOS and the gate electrode of a PMOS included in a CMOS semiconductor device are formed by using the same conductive material (e.g., the same kind of metal), it is difficult to ensure symmetrical threshold voltage characteristic and so on. In other words, it is difficult to form a configuration in which each of the gate electrodes of an NMOS and PMOS has the optimum work function value. To address this, there has also been proposed a scheme in which the gate electrodes of an NMOS and PMOS are formed by using different conductive materials. In addition, in order to achieve both optimization of the work function value of a gate electrode and low resistivity of the gate electrode, there has also been proposed the following method relating to formation of a gate electrode based on a damascene process. Specifically, in this method, initially a layer composed of a conductive material having a favorable work function value (for convenience, referred to as a work function control layer) is formed in a gate electrode formation opening (more specifically, in a bottom region and side region of the gate electrode formation opening that has the bottom region, the side region, and a center region surrounded by the bottom region and the side region). Subsequently, in the center region, another conductive material layer having lower resistivity (ratio resistivity) (for convenience, referred to as a center layer) is formed, so that a gate electrode is formed.
Miniaturization of insulated gate field effect transistors decreases the alignment margin in formation of contact plugs that are provided in an interlayer insulating layer covering a gate electrode and source/drain regions and are connected to the top surface of the gate electrode and the source/drain regions. Therefore, it is preferable to simultaneously form these contact plugs through a series of processes. The contact plugs are formed by forming in an interlayer insulating layer a contact plug formation opening having the bottom through which the top surface of a gate electrode is exposed and contact plug formation openings having the bottoms through which source/drain regions are exposed, and then burying tungsten or the like in these openings. The contact plug formation opening is formed by using known lithography and etching techniques.
Due to the difference in the height between the top surface of the gate electrode and the source/drain regions, the thickness of the interlayer insulating layer covering the gate electrode and the source/drain regions is relatively smaller on the gate electrode and relatively larger on the source/drain regions, at the timing after planarization treatment for the interlayer insulating layer. Consequently, in the formation of the contact plug formation openings in the interlayer insulating layer through a series of etching processes, the top surface of the gate electrode exposed at the bottom of the contact plug formation opening is subjected to the etching treatment for a relatively longer period compared with the source/drain regions exposed at the bottoms of the contact plug formation openings. Therefore, as the combination between the condition of the etching of the interlayer insulating layer and the material of the gate electrode, a combination that can offer a sufficiently high etching selection ratio may be required. Moreover, the material of the gate electrode is desirable to have sufficient resistance also against a series of chemical treatments performed after the etching.